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TI Glossary
1146 definitions by Texas Instruments Incorporated

Soft BitZero FillZero-Code Error DriftZero-Code ErrorXD0-XD31 Data Bus PinsXA0-XA13 Address PinsWrite Enable [WE] PinWordWindowWell-Defined ExpressionWATCH WindowWarm BootWait-State GeneratorWait StateWait QueueWaitingWafer Chip-Scale Package [WCSP]Voltage-Controlled Crystal Oscillator [VCXO]Voltage-Controlled Oscillator [VCO]Virtual MemoryVideo Random Access Memory [VRAM]Video Interface Palette [VIP]Video Graphics Array [VGA]Video DigitizerVideo ControllerVGA Pass-Through CableVertical Synchronization [VSYNC]Vertical Blanking [VBLNK]Vendor Unique [VU]Vector InstructionVector Dot ProductVoltage-Controlled Oscillator (VCO) Gain [KVCO]Variable-Patch Guided TransferVariableVaractor DiodeUser ModeUrgent Refresh CyclesUnsigned ValueUniversal Asynchronous Receiver and Transmitter [UART]UnionUnionUninitialized SectionUnified ModeUnder-Voltage Lockout [UVLO]Unconfigured MemoryTripleTrip CountTri-Graph SequenceTrickle Refresh CyclesTrap Vector Table Pointer [TVTP]Trap Vector Table [TVT]TrapTransparency on Source OperationTransparencyTransmitter Reset [XRST] BitTransmit Shift Register Empty [XSREMPTY] BitTransmit Reset [XRST] BitTransmit Register Empty Indicator [THRE] BitTransmit and Receive InterruptTransmit Ready [XRDY] BitTransmit Mode [TXM] BitTransmit Interrupt [XINT] Synchronous Serial PortTransmit Interrupt Serial PortTransmit Interrupt Mask [TIM] BitTransmit Frame Synchronization [FSX] PinTransmit Empty Indicator [TEMT] BitTransmit Clock I/O [CLKX] PinTransmit Buffer Half Transmitted [XH] BitTransmit [Tx]Transmission Control [TCOMP] bitTransient Voltage Suppressor [TVS]Transfer Controller [TC]Totem-Pole OutputTotal Harmonic Distortion And Noise [THD+N]Top Of Stack [TOS]Timer Stop Status [TSS] BitTimer Reload [TRB] BitTimer Prescaler Counter [PSC] BitsTimer Output [TOUT] PinTimer Interrupt [TINT] BitTimer Interrupt [TINT]Timer Divide-Down Register [TDDR] BitsTimerTime-Division Multiplexed (TDM) BitTime-Division Multiplexed [TDM]Time-Division Multiplexing [TDM]Time SlicingTightly-Coupled MultiprocessorThread of Execution.Text SectionTest and Control (TC) Flag BitTest Access Port [TAP]Temperature-Compensated Crystal Oscillator [TCXO]TDM Transmit Interrupt (TXNT) BitTDM Receive Interrupt (TRNT) BitTDM Data [TDAT]TDM Clock [TCLK]TDM Address [TADD]Task TableTask StateTask SchedulerTask PriorityTask InterruptTask IDTask FunctionTask ErrorTask DescriptorTask ArgumentTaskTARGET SystemTarget MemoryTargetTap PointTagT43 RatioT41 RatioT31 RatioSystem ShellSyntaxSynchronous Serial Port Receive InterruptSynchronous Power ConverterSyncSymbolic DebuggingSymbol TableSymbolic DebuggingSymbolSwitch Mode Power Supply [SMPS]Swap FileS-VHS-to-RCA Adapter CableSuspendSupervisor ModeSuper VHS (Vertical Helical Scan) [S-VHS]Substitution Symbol TableSubsectionSubroutineSub-Block MissSub-BlockStructureString TableStorage ClassStop BitStatus BitStatusStatic VariableStatic Random-Access Memory [SRAM]StateStart BitStack PointerStackStandalone SimulatorStandalone PreprocessorSram BanksSpur Gain [SG]Spurious AttenuationSplit MultiplySplit ModeSpinningSpectrum AnalyzerSource FileSoftware WriteSoftware StackSoftware PipeliningSoftware Development System [SWDS]Smith ChartSmall Outline (no lead) [SON]Slew RateSkewSingle ThreadedSingle StepSingle-Precision Unsigned-Integer FormatSingle-Precision Integer FormatSingle-Precision Floating-Point FormatSingle-Precision Floating-PointSingle Ended [SE]Single-Access RAM [SARAM]SimulatorSignal-To-Noise Ratio [SNR]Signaling Not-A-Number [SNaN]Sign-Extension Mode Bit [SXM]Sign ExtensionSign-ExtendSign BitSignal EventSignalSide EffectsShort Unsigned-Integer FormatShort Integer FormatShort OffsetShort-Immediate ValueShifterShell ProgramShared RAMsShared-Access Mode [SMOD] BitShared-Access Mode [SAM]Setbrk BitServerSerial Register Transfer [SRT] ControllerSerial Port Transmit Interrupt [XINT] BitSerial Port Receive Interrupt [RINT] BitSerial-Port InterfaceSerial PortSerial Data Transmit [DX] PinSerial Data Receive [DR] PinSerial Clock [SCLK]Serial Access Memory Mask [SAMMASK]Serial Access Memory Increment [SAMINC]Serial Access Memory [SAM]Sequential ModeSensitivitySemaphore TableSemi-Omnipresent PixelSemaphore IDSemaphoreSection Program Counter [SPC]Section HeaderSectionSCSI IDSCSI DeviceSCSI AddressSCSIScrollingScriptScratch-Pad RAMSchedulingSchedulerScan ChainScalar TypeSample RateSAM Overflow EventRuntime-Support LibraryRuntime-Support FunctionsRom Enable [ROMEN]Run AddressRow Address Strobe [RAS]Routing PortRound-Robin SchedulingRoot Mean Square [RMS] or [rms]ROM WidthROM ModelRuntime EnvironmentRipple-Carry Output SignalRightmost-Bit Change [rmbc]Rightmost 1 [rmo]Reverse Current Protection [RCP]Reverse Current Blocking [RCB]Reverse AssemblyReturn AddressRetraceResumeResource TableResource IDResolution Bandwidth [RBW]ResolutionReset VectorReset Pin (RS)Reset Asynchronous Serial Port [URST] BitResetReserved [R]Request MessageReply PortReply MessageRepeat ModeRepeat Counter [RC] RegisterRemote Procedure Call [RPC]RelocationRelative AccuracyRegister FileRegisterRefresh RateRefreshReference SpursReentrant CodeRedundant LoopsReduced Instruction Set Computer [RISC]ReconnectReclamation PortReceive Shift Register (Synchronous Serial Port) [RSR]Receiver Reset [RRST] BitReceiver Reset [RRST] BitReceiver Register Overrun Indicator Bit [OE]Receive Reset [RRST] BitReceive Register (Synchronous Serial Port) [SDTR]Receive Register (Asynchronous Serial Port) [ADTR]Receive Ready [RRDY] BitReceive [DR] Pin (Synchronous Serial Port)Receive [RX] Pin (Asynchronous Serial Port)Receive Interrupt (Synchronous Serial Port) [RINT]Receive Interrupt Mask Bit [RIM]Receive Interrupt (Asynchronous Serial Port)Receive Frame Synchronization [FSR] PinReceive FIFO Buffer Not Empty [RFNE] BitReceive (Synchronous Serial Port) [DR] PinReceive Clock Input (CLKR) PinReceive Buffer Half Received [RH] BitReceive [Rx]Real-Time SystemReal-Time ProcessingReal TimeReal ModeReady QueueReadyReadyRead/Write [R/W] PinRead Select Pin [RD]Read-Only Memory [ROM]RCA JackRCA ConnectorRaw dataRaster-OpRasterRandom-Access Memory Digital-to-Analog Converter [RAMDAC]Random-Access Memory [RAM]RAM Overlay (OVLY) bitRAM ModelRAM Enable Pin [RAMEN]Radio Frequency Front End [RFFE]R DividerQuality Factor [Q]Quiet Not-a-Number [QNaN]Quick Output Discharge [QOD]Quantum LevelsQuantization ErrorQuiet RunQiPushPulse Width Modulation [PWM]Pulse Frequency Modulation (or Mode) [PFM]Pulse Coded Modulation Mode [PCM] BitPulse Code Modulation [PCM]Pulldown MenuProtected ModePrologProgrammed I/O [PIO] ModeProgrammable Read-Only Memory [PROM]Programmable Logic Array [PLA]Program-Space Upper Wait-State [PSUWS] BitProgram-Space Wait-State [PSWS] BitProgram Select Pin [PS]Program Read Bus [PRDB]Program MemoryProgram Memory Address [PMA]Program-Level OptimizationProgram Flow Control UnitProgram/Data Wait-State Register [PDWSR]Program Counter [PC] FieldProgram Counter [PC]Program ControllerProgram Control LogicProgram-Address Generation LogicProgram Address Register [PAR]Program Address Bus [PAB]ProfilingProfile WindowProduct Shift Mode [PM] BitsProduct-Scaling ShifterProduct Register [PREG]Processor NodeProcessor Mode Status Register [PMST]ProcessorPrivate ContextPrinted-Circuit Assembly [PCA]Present FlagPrescaler Counter [PSC]PrescalerPreprocessorPrefetch Counter [PFC]PreemptPragmaPower Transmitting and Power Receiving [Tx], [Rx]Power-Supply Rejection RatioPower-On Reset [POR]Power Management Unit [PMU]Power-Down ModePostscalerPort TablePort IDPort AddressPortPorchPOPPollPointPlayback ModePixel DroppingPixel-Block Transfer [PIXBLT]PixelPitchPipeliningPipeline StallPipelined ModePipelined-Loop PrologPipelined-Loop EpilogPipelinePin-to-Pin On Resistance [RON]Pin Grid Array [PGA]Phase Noise FloorPhase NoisePhase Margin [Ø]Phase-Locked Loop [PLL]Phase-Frequency Detector [PFD]Phase DetectorPhase Alternation Line [PAL]Physical AddressPersonal Computer [PC]Peripheral Component Interconnect [PCI]Input Clock Signal (CLKIN]Init-ListInitiatorInitialized SectionInitialization at Load TimeInitdb.batInit.cmdIndustry Standard Architecture [ISA]Indirect CallIndirect AddressingIncremental LinkingImmediate Operand, Immediate ValueImmediate AddressingIEEE ModeIEEE 1149.1 StandardIEEE-754 StandardIEEE-754 Floating-Point UnitIdentifier [ID]HPI Control Register Low [HPICL] ByteHPI Control Register High [HPICH] ByteHPI Address Register Low [HPIAL] ByteHPI Address Register High [HPIAH] ByteHousekeepingHot-Plug Detect [HPD]Host Port Interface [HPI]Host-Only Mode [HOM]Horizontal Synchronization [HSYNC]Horizontal Blanking [HBLNK]HoleHold OperationHold Mode [HM] BitHOLD Acknowledge Signal [HOLDA]HoldHitHigh-Level Language DebuggingHigh-Impedance Mode – [HiZ] ModeHex Conversion UtilityHex Command FileHeapHardware InterruptHalfwordGuide TableGuided TransferGroupGround StrapGrayscale or GreyscaleGraphics Output Monitor CableGraphical User Interface [GUI]Global TransferGlobal SymbolGlobal PortGlobal LegalGlobal Interrupt Enable [GIE]Global-Data Memory SpaceGlobal Address UnitGeneral-Purpose Input/Output [GPIO] PinsGamma Optimization ParameterGain Temperature CoefficientGain StageGain ErrorFull-Scale Range [FSR]Full-Scale Error DriftFull-Scale ErrorFunction InliningFront PorchFrequency Tolerance [tol]Frequency synthesizerFrequency Jump [Fj]Free BitFraming Error Indicator [FE] BitFraming ErrorFrame TimerFrame Synchronization [Frame Sync] PulseFrame Synchronization [Frame Sync] ModeFrame Synchronization Polarity [FSP] BitFrame Synchronization Mode [FSM] BitFrame LockFrame Ignore [FIG] BitFrameFractional SpurFractional N PLLFractional Modulus [FDEN]Format Extension [FE] BitFormat [FO] BitForeign NodeFloating-Point Unit [FPU]Floating-Point Multiply Unit BusyFloating-Point Exception Handler RoutineFloating-Point EmptyFloating-Point Add Unit BusyFlash MemoryFlag OffsetsFlagFixed-Patch Guided TransferFirst In, First Out [FIFO]Fill-with-Value TransferFile WindowFile-Level OptimizationFile HeaderFIFO Transmit-Interrupt Bits [FT0], [FT1]FIFO Receive-Interrupt Bits [FR0], [FR1]FIFO FlagFIFO BufferField Replicate MoveField Extract MoveField-Effect Transistor [FET]FieldFetch StageFetch PacketFetch, Execute, Access [FEA] Pipeline SequenceFetch, Address, Execute [FAE] Pipeline SequenceFetchFET Only on Resistance [RDS(on)]FaultFast ModeFast Fourier Transform [FFT]External SymbolExternally Initiated Packet Transfer [XPT]External InterruptExternal Flag [XF] Pin Status BitExternal Flag [XF] PinExternal Access Active Strobe [STRB]Extended-Precision RegisterExtended-Precision Floating-Point FormatExtended Arithmetic Logic Unit [EALU]ExpressionExport Control Classification Number [ECCN]Export Control Notice [ECN]ExpanderExit-ListExecutiveExecute StageExecute PhaseExecute PacketExecutable ModuleException RegisterException HandlerException FlagExceptionEvaluation Module [EVM]Event RegisterEvent PinEvent FlagEventErasable Programmable Read-Only Memory [EPROM]Equivalent Series Resistance [ESR]EpilogEnvironment VariableEnvelope Tracking [ET]Entry PointEnable Multiple TREGs (TRM) BitEnable Extra Index Register (NDX) BitEmurstEmulatorShort ImmediateShort-Floating-Point FormatEMIF CE SpaceElectrostatic Discharge [ESD]Electromagnetic Interference [EMI]EALU||ROTATEDynamic Random-Access Memory [DRAM]Dynamic Power-Path Management [DPPM]Dynamic Power Management [DPM]Dynamic Memory AllocationDummy CycleDual In-line Package [DIP]DSP-to-Host Processor Interrupt [HINT] BitDSP Interrupt (DSPINT) BitDoublewordDouble-Precision Floating-PointDouble BufferingDot ClockD_OPTIONSDMA CoprocessorDivide-Down ValueDISP WindowDisplay ModeDisplay AreaDiscrete Cosine Transform [DCT]Discontinuous Conduction Mode [DCM]DiscontinuityDisconnectDISASSEMBLY WindowDisassemblyDirty FlagDirect Memory Access Mode [DMA Mode]Direct Memory Access [DMA]DirectiveDirect External Access [DEA]Direct CallDirect AddressingDirect Address Bus [DAB]Diode Emulation Mode [DEM]DIO0-DIO3 BitsDIN ConnectorDimensioned TransferDigitizerDigital Visual Interface [DVI]Digital-to-Analog Glitch Impulse During Code ChangeDigital-to-Analog Converter [DAC]Digital-to-Analog [D/A]Digital Signal Processor [DSP]Digital MixingDigital Micromirror Device [DMD]Digital Loopback [DLB] BitDigital Loopback [DLB] ModeDigital FeedthroughDifferential Nonlinearity [DNL]Die-Sized Ball Grid Array [DSBGA]DhrystonesDevice DriverDeutsch Industrie Norm [DIN]Detect Complete [ADC] BitDestination PortDestination ControllerDenormalDelta-Sigma PLLDelta-Interrupt Mask [DIM] BitDelta InterruptDelta-Guided TransferDelay SlotDefault TaskDecode PhaseDebuggerDeassertDead Zone Elimination CircuitryDead ZoneData Write Bus [DWEB]Data Unit OperationData UnitData Terminal Ready [DTR]Data-Space Wait-State [DSWS] BitData SizeData Read Bus [DRDB]Data-Read Address Bus [DRAB]Data RamData PageData Memory Select Pin [DS]Data Memory Page 0Data Memory Page Pointer [DP] BitsData Memory Address [DMA] BitsData MemoryData-Display WindowsData-Cache Reset [DCR]Data CacheData BusData-Address Generation Logic.data sectionDamping FactorDAC Output Noise DensityDAC Output NoiseD0- Dn Data Bus PinsCycleCurrent-field CursorCurrent Data PageCrystal Reference [XTAL]Cross-reference ListingCross-reference ListerCrossbarCPU WindowCPU CycleCounting SemaphoreC OptimizerConvolutionControl Voltage [VTUNE]Continuous Time ApproximationContinuos Conduction Mode [CCM]Continuous ModeContext Save and RestoreContentionConstantConnectorConnectConfigured MemoryConfiguration Control [CNF] Bitconfig.sysConditional SourceConditional ProcessingCompression and Decompression [codec]Compressed and Expanded [Companded]Composite Video DisplayComposite Video [CVBS]Composite Synchronization [CSYNC]Composite Blanking [CBLNK]Composite Area [CAREA]Complementary Metal Oxide Semiconductor [CMOS]CompilerComparison Frequency [FCOMP]Common Object File Format [COFF]CommentCOMMAND WindowCommand-line InterfaceCommand-line CursorCommand LineCommand InterpreterCommand FileCommand Descriptor Block [CDB]CommandColumn Mask [COLMASK]Column Address Strobe [CAS]Cold BootCOFF magic numberCoder-decoder [codec]Code GeneratorCode-Display WindowsCodeClock Polarity [CLKP] BitClock ModesClock Mode [MCM] BitClock Mode (Clock Generator)Clock CycleCLKMOD PinClientClass-specific ArithmeticsClass-Independent ArithmeticsCircular Buffer 2 Enable [CENB2] BitCircular Buffer 1 Enable [CENB1] BitCircular AddressingChrominanceChip Scale Package [CSP]ChildrenCharge Pump Gain [KΦ]Charge PumpChannel-and-Channel SpacingChannel-to-Channel DC CrosstalkChannel-to-Channel CrosstalkCentral Processing Unit [CPU]Central Arithmetic Logic Unit [CALU]Centiwatt-hour [cWh]C CompilerCIO0-CIO3 BitsCastingCarry Bit [C Bit]Capture ModeCALLS WindowCalibrate A Detect [CAD] BitCache Sub-blockCache MissCache HitCache FlushCache CoherencyCache CleanCache BlockCacheC Programming LanguageByte-Ordering Bit [BOB]ByteButterflyBus WatchingBus Request [BR] PinBurst ModeBulletin Board System [BBS]Buffer PoolBuffered Serial Port [BSP]Bubble.bss sectionBridge-Tied Load [BTL]BreakpointBreak Interrupt [BI] BitBranchBoundary ScanBOOT pinBootloaderBootBloomerBlock WriteBlock Repeat Active Flag [BRAF] BitBlock MissBlockedBlanking PulseBlanking AreaBlankingPeripheral CablePeripheral BusPeriod [PRD] RegisterPeriodic EventPending InterruptPC RegisterPatchPartial LinkingParserParameter TableParameter RAMParallel TransfersParallel Processor Command InterfaceParallel Processor [PP]Parallel PortParallel Logic Unit [PLU]Parallel Debug Manager [PDM]Parallel Bridge-Tied Load [PBTL]Packet Transfer RequestPacket Transfer Options FieldPacket Transfer [PT]Packet Transfer Access Mode [PAM]PacketPacked HalfwordsPacked BytesPx64Overflow (Synchronous Serial Port) [OV] BitOvershootOverrunOverlay ModeOverlay PageOverflow Mode [OVM] BitOverflow ModeOverflow Flag [OV] BitOverflow (Synchronous Serial Port)Overflow (Register)OverflowOver-Current Protection [OCP]Output Voltage Settling TimeOutput SectionOutput ModuleOutput Data-Scaling ShifterOptional HeaderOptionsOptimizationOptimizerOperation ClassOperationOperand-Fetch PhaseOperandOpen Loop Transfer Function [G(s)]Open-Collector OutputOperation Code [Opcode]On-The-Go [OTG]On-Chip AddressOn-ChipOffset-Guided TransferOffset-Guided Look-up Table TransferOffset Error DriftOffset ErrorOff-Chip AddressOff-ChipObject LibraryObject Format ConverterObject FileNot Acknowledge [NACK]Non-Synchronous Power ConverterNonmaskable Interrupt NMINoninterlaced ModeNoninterlaced Graphics ModeNon-D OperandNode NumberNode-Local Port IDNode-Global Port IDNodeNext Program Address Register [NPAR]Next Auxiliary RegisterNested InterruptNegative Temperature Coefficient [NTC]Natural Frequency [ωη]National Television Standards Committee [NTSC]Named SectionN DividerMutual ExclusionMultitasking ExecutiveMultisync MonitorMultiply And Accumulate [MAC]Multiplier MULTMultiple-Halfword ArithmeticMultiple-Byte ArithmeticMultiple ArithmeticMultiplexingMultimedia Video Processor [MVP]MP/MC PinMaster Processor Compiler [MPCL]Moving Picture Experts Group Standard [MPEG]Mouse CursorMotherboardMost Significant Byte [MSByte]Most Significant Bit [MSB]MonotonicityMono ModeMonitor TimingModulation Index [ß]Modulation Domain AnalyzerMode L StatementMode BitMobile Industry Processor Interface [MIPI]MnemonicMixed ModeMissMiscellaneous OperationMillion Instructions Per Second [MIPS]Minimal ModeMini-Din ConnectorMultiple Instruction Stream, Multiple Data Stream [MIMD]Millions of Floating-point Operations Per Second [MFLOPS]Microstack [MSTACK]Microprocessor ModeMicroprocessor/Microcomputer [MP/MC] BitMicroprocessorMicrocomputer ModeMicrocomputerMicrocall Stack [MCS]Metric ParametersMessage-Routing TableMessage InterruptMessage Heade RMessage EventMessage Buffer PoolMerge ModeMenu BarMemory WindowMemory WidthMemory StallMemory-Mapped RegisterMemory MapMemberMegahertz [MHz]MCBL/MP PinMaximum Power Point (Tracking) [MPP(T)]Master PhaseMaster Clock Output Signal [CLKOUT1]MaskingMask GeneratorMaskable InterruptMap FileMantissaMailboxMagic NumberMacro LibraryMacro ExpansionMacro DefinitionMacro CallMacroLuminanceLRU Cache ReplacementLRAM2 ProcessorLRAM1 ProcessorLRAM0 ProcessorLPRAM ProcessorLow-Voltage Differential Signaling [LVDS]Low-Pass Filter [LPF]Low Dropout [LDO]Low Color Register Cycle [LCR]Loop UnrollingLoop Gain Constant [K]Loop Filter Impedance [G(s)]Loop FilterLoop Bandwidth [ωc or Fc]LoopLook-Up Table [LUT]Long OffsetLong-Immediate ValueLong ImmediateLogic PhaseLogical Unit Number [LUN]Logical UnitLogical AddressLock TimeLocked PLLLocal TransferLocal RAMLocal PortLocal NodeLocal LegalLocal Data SpaceLocal BusLocal Address UnitLoaderLoad Color Register [LCR] CycleLoad AddressLoadLive OutLive InLittle EndianListing FileLinker Command FileLinkerLine Number EntryLine DroppingLinear AssemblyLight Emitting Device [LED]Leftmost-Bit Change [LMBC]Leftmost 1 [LMo]Least-Significant Byte [LSByte]Least-Significant Bit [LSB]LD0–LDn Data Bus PinsLatencyLatch PhaseLabelLA0–LAn Address PinsKernighan and Ritchie [K & R]Kernel ResourceKernelJoint Test Action Group [JTAG]Joint Photographic Experts Group [JPEG] StandardJapan Electronics and Information Technology Industries Association [JEITA]I/O SwitchesI/O-Space Wait-State Bits [ISWS]I/O Space Select Pin [IS]IO0-IO3 PinsIO0-IO3 BitsINTn PinInterrupt Vector Table Pointer [IVTP]Interrupt Vector Table [IVT]Interrupt Vector Pointer [IPTR] BitsInterrupt Vector LocationInterrupt VectorInterrupt-Trap Table Pointer [ITTP]Interrupt Service Table [IST]Interrupt Service Routine [ISR]Interrupt Service Fetch Packet [ISFP]Interrupt Mode [INTM] BitInterrupt LatencyInterrupt Acknowledge Signal (IACK]InterruptInterprocessor CommandInternode Message ManagerInternal Transmit Clock Division Factor (CLKDV] BitsInternal Memory BankInternal InterruptInternal Data Memory BlockInternal AddressInterlist UtilityInterlaced ModeInter-Integrated Circuit (Serial Communication Bus) [I2C]Inter-Device Sound [I2S]Integrated Services Digital Network [ISDN]Integrated PreprocessorIntegrated Circuit [IC]Integral Nonlinearity [INL]Instruction WordInstruction PortInstruction Pointer Execution [IPE]Instruction Pointer Address [IPA]Instruction Pointer [IP]Instruction-Fetch PhaseInstruction-Execute PhaseInstruction-Decode PhaseInstruction-Cache Reset [ICR]Instruction CacheInstruction BusInstructionInput SectionInput Data-Scaling ShifterBits Per Pixel [BPP]Bit-Reversed Indexed AddressingBit-Reversed AddressingBit PlaneBitmapBit DetectionBit-Aligned Block Transfer [bitBLT]BIO PinBindingBill of Materials [BOM]Big-EndianBIG BitBenchmarkingBattery Management Unit [BMU]Batch FileBasic Rate Service of ISDN [BRI]Base Set BooleansBase Set ArithmeticsBase Set ALUsBaseBarrel ShifterBarrel RotatorBack PorchB2 On-Chip BlockB1 On-Chip BlockB0 On-Chip BlockAuxiliary Register Pointer Buffer [ARB]Auxiliary Register Pointer [ARP]Auxiliary Register File Bus [AFB]Auxiliary Register Buffer [ARB] BitsAuxiliary Register Arithmetic Unit [ARAU]Auxiliary EntryAutomatic Gain Control [AGC]Autoinitialization at RuntimeAutoinitialization at Load TimeAutoinitializationAutoexec.batAutocalibrationAutobuffering Unit [ABU]Autobuffering Transmitter Halt [HALTX] BitAutobuffering Transmitter Enable [BXE] BitAutobuffering Receiver Halt [HALTR] BitAutobuffering Receiver Enable [BRE] BitAuto ModeAudio Breakout CableAttributeAttenuation Index [ATTEN]Asynchronous Transmit [TX] PinAssignment StatementAssertAssembly-Time ConstantAssembly OptimizerAssembly ModeAssembly Language InstructionsAssembly LanguageAssemblerAssembleArithmetic Logic Unit [ALU]Argument BufferArchiverArchive LibraryArchitectureApplication Programming Interface [API]AnnulAngle of Incidence [AOI]Analog-to-Digital Converter [ADC]Analog-to-Digital [A/D]Analog MixingAnalog Interface Circuit [AIC]American Standard Code for Information Interchange, 1968 [ASCII]American National Standards Institute (ANSI) [ANSI C]American National Standards Institute [ANSI]ALU OperationALU Function ModifierALU FunctionAllocation NodeAllocationAlignmentAliasingAlias DisambiguationA-Law CompandingAggregate TypeAdvanced Gas Gauge [AGG]Administrative PrivilegesAddress Visibility [AVIS] BitAddress Unit ArithmeticAddress UnitAddress StageAddressing ModeAddressActive WindowActive TimeActive Noise Cancellation [ANC]Active Current Assist and Analog Bypass [ACB]Acknowledge [ACK]Accumulator Low Byte [ACCL]Accumulator High Byte [ACCH]Accumulator Buffer [ACCB]Accumulator [ACC]Access StageAbsolute ListerAbsolute AddressA0-An Address Pins
Date
2016-03-01
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