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TI Glossary
1146 definitions by Texas Instruments Incorporated

A0-An Address PinsAbsolute AddressAbsolute ListerAccess StageAccumulator [ACC]Accumulator Buffer [ACCB]Accumulator High Byte [ACCH]Accumulator Low Byte [ACCL]Acknowledge [ACK]Active Current Assist and Analog Bypass [ACB]Active Noise Cancellation [ANC]Active TimeActive WindowAddressAddressing ModeAddress StageAddress UnitAddress Unit ArithmeticAddress Visibility [AVIS] BitAdministrative PrivilegesAdvanced Gas Gauge [AGG]Aggregate TypeA-Law CompandingAlias DisambiguationAliasingAlignmentAllocationAllocation NodeALU FunctionALU Function ModifierALU OperationAmerican National Standards Institute [ANSI]American National Standards Institute (ANSI) [ANSI C]American Standard Code for Information Interchange, 1968 [ASCII]Analog Interface Circuit [AIC]Analog MixingAnalog-to-Digital [A/D]Analog-to-Digital Converter [ADC]Angle of Incidence [AOI]AnnulApplication Programming Interface [API]ArchitectureArchive LibraryArchiverArgument BufferArithmetic Logic Unit [ALU]AssembleAssemblerAssembly LanguageAssembly Language InstructionsAssembly ModeAssembly OptimizerAssembly-Time ConstantAssertAssignment StatementAsynchronous Transmit [TX] PinAttenuation Index [ATTEN]AttributeAudio Breakout CableAutobuffering Receiver Enable [BRE] BitAutobuffering Receiver Halt [HALTR] BitAutobuffering Transmitter Enable [BXE] BitAutobuffering Transmitter Halt [HALTX] BitAutobuffering Unit [ABU]AutocalibrationAutoexec.batAutoinitializationAutoinitialization at Load TimeAutoinitialization at RuntimeAutomatic Gain Control [AGC]Auto ModeAuxiliary EntryAuxiliary Register Arithmetic Unit [ARAU]Auxiliary Register Buffer [ARB] BitsAuxiliary Register File Bus [AFB]Auxiliary Register Pointer [ARP]Auxiliary Register Pointer Buffer [ARB]B0 On-Chip BlockB1 On-Chip BlockB2 On-Chip BlockBack PorchBarrel RotatorBarrel ShifterBaseBase Set ALUsBase Set ArithmeticsBase Set BooleansBasic Rate Service of ISDN [BRI]Batch FileBattery Management Unit [BMU]BenchmarkingBIG BitBig-EndianBill of Materials [BOM]BindingBIO PinBit-Aligned Block Transfer [bitBLT]Bit DetectionBitmapBit PlaneBit-Reversed AddressingBit-Reversed Indexed AddressingBits Per Pixel [BPP]BlankingBlanking AreaBlanking PulseBlockedBlock MissBlock Repeat Active Flag [BRAF] BitBlock WriteBloomerBootBootloaderBOOT pinBoundary ScanBranchBreak Interrupt [BI] BitBreakpointBridge-Tied Load [BTL].bss sectionBubbleBuffered Serial Port [BSP]Buffer PoolBulletin Board System [BBS]Burst ModeBus Request [BR] PinBus WatchingButterflyByteByte-Ordering Bit [BOB]CacheCache BlockCache CleanCache CoherencyCache FlushCache HitCache MissCache Sub-blockCalibrate A Detect [CAD] BitCALLS WindowCapture ModeCarry Bit [C Bit]CastingC CompilerCentiwatt-hour [cWh]Central Arithmetic Logic Unit [CALU]Central Processing Unit [CPU]Channel-and-Channel SpacingChannel-to-Channel CrosstalkChannel-to-Channel DC CrosstalkCharge PumpCharge Pump Gain [KΦ]ChildrenChip Scale Package [CSP]ChrominanceCIO0-CIO3 BitsCircular AddressingCircular Buffer 1 Enable [CENB1] BitCircular Buffer 2 Enable [CENB2] BitClass-Independent ArithmeticsClass-specific ArithmeticsClientCLKMOD PinClock CycleClock Mode (Clock Generator)Clock Mode [MCM] BitClock ModesClock Polarity [CLKP] BitCodeCode-Display WindowsCode GeneratorCoder-decoder [codec]COFF magic numberCold BootColumn Address Strobe [CAS]Column Mask [COLMASK]CommandCommand Descriptor Block [CDB]Command FileCommand InterpreterCommand LineCommand-line CursorCommand-line InterfaceCOMMAND WindowCommentCommon Object File Format [COFF]Comparison Frequency [FCOMP]CompilerComplementary Metal Oxide Semiconductor [CMOS]Composite Area [CAREA]Composite Blanking [CBLNK]Composite Synchronization [CSYNC]Composite Video [CVBS]Composite Video DisplayCompressed and Expanded [Companded]Compression and Decompression [codec]Conditional ProcessingConditional Sourceconfig.sysConfiguration Control [CNF] BitConfigured MemoryConnectConnectorConstantContentionContext Save and RestoreContinuos Conduction Mode [CCM]Continuous ModeContinuous Time ApproximationControl Voltage [VTUNE]ConvolutionC OptimizerCounting SemaphoreC Programming LanguageCPU CycleCPU WindowCrossbarCross-reference ListerCross-reference ListingCrystal Reference [XTAL]Current Data PageCurrent-field CursorCycleD0- Dn Data Bus PinsDAC Output NoiseDAC Output Noise DensityDamping FactorData-Address Generation LogicData BusData CacheData-Cache Reset [DCR]Data-Display WindowsData MemoryData Memory Address [DMA] BitsData Memory Page 0Data Memory Page Pointer [DP] BitsData Memory Select Pin [DS]Data PageData RamData-Read Address Bus [DRAB]Data Read Bus [DRDB].data sectionData SizeData-Space Wait-State [DSWS] BitData Terminal Ready [DTR]Data UnitData Unit OperationData Write Bus [DWEB]Dead ZoneDead Zone Elimination CircuitryDeassertDebuggerDecode PhaseDefault TaskDelay SlotDelta-Guided TransferDelta InterruptDelta-Interrupt Mask [DIM] BitDelta-Sigma PLLDenormalDestination ControllerDestination PortDetect Complete [ADC] BitDeutsch Industrie Norm [DIN]Device DriverDhrystonesDie-Sized Ball Grid Array [DSBGA]Differential Nonlinearity [DNL]Digital FeedthroughDigital Loopback [DLB] BitDigital Loopback [DLB] ModeDigital Micromirror Device [DMD]Digital MixingDigital Signal Processor [DSP]Digital-to-Analog Converter [DAC]Digital-to-Analog [D/A]Digital-to-Analog Glitch Impulse During Code ChangeDigital Visual Interface [DVI]DigitizerDimensioned TransferDIN ConnectorDIO0-DIO3 BitsDiode Emulation Mode [DEM]Direct Address Bus [DAB]Direct AddressingDirect CallDirect External Access [DEA]DirectiveDirect Memory Access [DMA]Direct Memory Access Mode [DMA Mode]Dirty FlagDisassemblyDISASSEMBLY WindowDisconnectDiscontinuityDiscontinuous Conduction Mode [DCM]Discrete Cosine Transform [DCT]Display AreaDisplay ModeDISP WindowDivide-Down ValueDMA CoprocessorD_OPTIONSDot ClockDouble BufferingDouble-Precision Floating-PointDoublewordDSP Interrupt (DSPINT) BitDSP-to-Host Processor Interrupt [HINT] BitDual In-line Package [DIP]Dummy CycleDynamic Memory AllocationDynamic Power Management [DPM]Dynamic Power-Path Management [DPPM]Dynamic Random-Access Memory [DRAM]EALU||ROTATEElectromagnetic Interference [EMI]Electrostatic Discharge [ESD]EMIF CE SpaceEmulatorEmurstEnable Extra Index Register (NDX) BitEnable Multiple TREGs (TRM) BitEntry PointEnvelope Tracking [ET]Environment VariableEpilogEquivalent Series Resistance [ESR]Erasable Programmable Read-Only Memory [EPROM]Evaluation Module [EVM]EventEvent FlagEvent PinEvent RegisterExceptionException FlagException HandlerException RegisterExecutable ModuleExecute PacketExecute PhaseExecute StageExecutiveExit-ListExpanderExport Control Classification Number [ECCN]Export Control Notice [ECN]ExpressionExtended Arithmetic Logic Unit [EALU]Extended-Precision Floating-Point FormatExtended-Precision RegisterExternal Access Active Strobe [STRB]External Flag [XF] PinExternal Flag [XF] Pin Status BitExternal InterruptExternally Initiated Packet Transfer [XPT]External SymbolFast Fourier Transform [FFT]Fast ModeFaultFetchFetch, Address, Execute [FAE] Pipeline SequenceFetch, Execute, Access [FEA] Pipeline SequenceFetch PacketFetch StageFET Only on Resistance [RDS(on)]FieldField-Effect Transistor [FET]Field Extract MoveField Replicate MoveFIFO BufferFIFO FlagFIFO Receive-Interrupt Bits [FR0], [FR1]FIFO Transmit-Interrupt Bits [FT0], [FT1]File HeaderFile-Level OptimizationFile WindowFill-with-Value TransferFirst In, First Out [FIFO]Fixed-Patch Guided TransferFlagFlag OffsetsFlash MemoryFloating-Point Add Unit BusyFloating-Point EmptyFloating-Point Exception Handler RoutineFloating-Point Multiply Unit BusyFloating-Point Unit [FPU]Foreign NodeFormat Extension [FE] BitFormat [FO] BitFractional Modulus [FDEN]Fractional N PLLFractional SpurFrameFrame Ignore [FIG] BitFrame LockFrame Synchronization [Frame Sync] ModeFrame Synchronization [Frame Sync] PulseFrame Synchronization Mode [FSM] BitFrame Synchronization Polarity [FSP] BitFrame TimerFraming ErrorFraming Error Indicator [FE] BitFree BitFrequency Jump [Fj]Frequency synthesizerFrequency Tolerance [tol]Front PorchFull-Scale ErrorFull-Scale Error DriftFull-Scale Range [FSR]Function InliningGain ErrorGain StageGain Temperature CoefficientGamma Optimization ParameterGeneral-Purpose Input/Output [GPIO] PinsGlobal Address UnitGlobal-Data Memory SpaceGlobal Interrupt Enable [GIE]Global LegalGlobal PortGlobal SymbolGlobal TransferGraphical User Interface [GUI]Graphics Output Monitor CableGrayscale or GreyscaleGround StrapGroupGuided TransferGuide TableHalfwordHardware InterruptHeapHex Command FileHex Conversion UtilityHigh-Impedance Mode – [HiZ] ModeHigh-Level Language DebuggingHitHoldHOLD Acknowledge Signal [HOLDA]Hold Mode [HM] BitHold OperationHoleHorizontal Blanking [HBLNK]Horizontal Synchronization [HSYNC]Host-Only Mode [HOM]Host Port Interface [HPI]Hot-Plug Detect [HPD]HousekeepingHPI Address Register High [HPIAH] ByteHPI Address Register Low [HPIAL] ByteHPI Control Register High [HPICH] ByteHPI Control Register Low [HPICL] ByteIdentifier [ID]IEEE 1149.1 StandardIEEE-754 Floating-Point UnitIEEE-754 StandardIEEE ModeImmediate AddressingImmediate Operand, Immediate ValueIncremental LinkingIndirect AddressingIndirect CallIndustry Standard Architecture [ISA]Init.cmdInitdb.batInitialization at Load TimeInitialized SectionInitiatorInit-ListInput Clock Signal (CLKIN]Input Data-Scaling ShifterInput SectionInstructionInstruction BusInstruction CacheInstruction-Cache Reset [ICR]Instruction-Decode PhaseInstruction-Execute PhaseInstruction-Fetch PhaseInstruction Pointer Address [IPA]Instruction Pointer Execution [IPE]Instruction Pointer [IP]Instruction PortInstruction WordIntegral Nonlinearity [INL]Integrated Circuit [IC]Integrated PreprocessorIntegrated Services Digital Network [ISDN]Inter-Device Sound [I2S]Inter-Integrated Circuit (Serial Communication Bus) [I2C]Interlaced ModeInterlist UtilityInternal AddressInternal Data Memory BlockInternal InterruptInternal Memory BankInternal Transmit Clock Division Factor (CLKDV] BitsInternode Message ManagerInterprocessor CommandInterruptInterrupt Acknowledge Signal (IACK]Interrupt LatencyInterrupt Mode [INTM] BitInterrupt Service Fetch Packet [ISFP]Interrupt Service Routine [ISR]Interrupt Service Table [IST]Interrupt-Trap Table Pointer [ITTP]Interrupt VectorInterrupt Vector LocationInterrupt Vector Pointer [IPTR] BitsInterrupt Vector Table [IVT]Interrupt Vector Table Pointer [IVTP]INTn PinIO0-IO3 BitsIO0-IO3 PinsI/O Space Select Pin [IS]I/O-Space Wait-State Bits [ISWS]I/O SwitchesJapan Electronics and Information Technology Industries Association [JEITA]Joint Photographic Experts Group [JPEG] StandardJoint Test Action Group [JTAG]KernelKernel ResourceKernighan and Ritchie [K & R]LA0–LAn Address PinsLabelLatch PhaseLatencyLD0–LDn Data Bus PinsLeast-Significant Bit [LSB]Least-Significant Byte [LSByte]Leftmost 1 [LMo]Leftmost-Bit Change [LMBC]Light Emitting Device [LED]Linear AssemblyLine DroppingLine Number EntryLinkerLinker Command FileListing FileLittle EndianLive InLive OutLoadLoad AddressLoad Color Register [LCR] CycleLoaderLocal Address UnitLocal BusLocal Data SpaceLocal LegalLocal NodeLocal PortLocal RAMLocal TransferLocked PLLLock TimeLogical AddressLogical UnitLogical Unit Number [LUN]Logic PhaseLong ImmediateLong-Immediate ValueLong OffsetLook-Up Table [LUT]LoopLoop Bandwidth [ωc or Fc]Loop FilterLoop Filter Impedance [G(s)]Loop Gain Constant [K]Loop UnrollingLow Color Register Cycle [LCR]Low Dropout [LDO]Low-Pass Filter [LPF]Low-Voltage Differential Signaling [LVDS]LPRAM ProcessorLRAM0 ProcessorLRAM1 ProcessorLRAM2 ProcessorLRU Cache ReplacementLuminanceMacroMacro CallMacro DefinitionMacro ExpansionMacro LibraryMagic NumberMailboxMantissaMap FileMaskable InterruptMask GeneratorMaskingMaster Clock Output Signal [CLKOUT1]Master PhaseMaster Processor Compiler [MPCL]Maximum Power Point (Tracking) [MPP(T)]MCBL/MP PinMegahertz [MHz]MemberMemory MapMemory-Mapped RegisterMemory StallMemory WidthMemory WindowMenu BarMerge ModeMessage Buffer PoolMessage EventMessage Heade RMessage InterruptMessage-Routing TableMetric ParametersMicrocall Stack [MCS]MicrocomputerMicrocomputer ModeMicroprocessorMicroprocessor/Microcomputer [MP/MC] BitMicroprocessor ModeMicrostack [MSTACK]Million Instructions Per Second [MIPS]Millions of Floating-point Operations Per Second [MFLOPS]Mini-Din ConnectorMinimal ModeMiscellaneous OperationMissMixed ModeMnemonicMobile Industry Processor Interface [MIPI]Mode BitMode L StatementModulation Domain AnalyzerModulation Index [ß]Monitor TimingMono ModeMonotonicityMost Significant Bit [MSB]Most Significant Byte [MSByte]MotherboardMouse CursorMoving Picture Experts Group Standard [MPEG]MP/MC PinMultimedia Video Processor [MVP]Multiple ArithmeticMultiple-Byte ArithmeticMultiple-Halfword ArithmeticMultiple Instruction Stream, Multiple Data Stream [MIMD]MultiplexingMultiplier MULTMultiply And Accumulate [MAC]Multisync MonitorMultitasking ExecutiveMutual ExclusionNamed SectionNational Television Standards Committee [NTSC]Natural Frequency [ωη]N DividerNegative Temperature Coefficient [NTC]Nested InterruptNext Auxiliary RegisterNext Program Address Register [NPAR]NodeNode-Global Port IDNode-Local Port IDNode NumberNon-D OperandNoninterlaced Graphics ModeNoninterlaced ModeNonmaskable Interrupt NMINon-Synchronous Power ConverterNot Acknowledge [NACK]Object FileObject Format ConverterObject LibraryOff-ChipOff-Chip AddressOffset ErrorOffset Error DriftOffset-Guided Look-up Table TransferOffset-Guided TransferOn-ChipOn-Chip AddressOn-The-Go [OTG]Open-Collector OutputOpen Loop Transfer Function [G(s)]OperandOperand-Fetch PhaseOperationOperation ClassOperation Code [Opcode]OptimizationOptimizerOptional HeaderOptionsOutput Data-Scaling ShifterOutput ModuleOutput SectionOutput Voltage Settling TimeOver-Current Protection [OCP]OverflowOverflow Flag [OV] BitOverflow ModeOverflow Mode [OVM] BitOverflow (Register)Overflow (Synchronous Serial Port)Overflow (Synchronous Serial Port) [OV] BitOverlay ModeOverlay PageOverrunOvershootPacked BytesPacked HalfwordsPacketPacket Transfer Access Mode [PAM]Packet Transfer Options FieldPacket Transfer [PT]Packet Transfer RequestParallel Bridge-Tied Load [PBTL]Parallel Debug Manager [PDM]Parallel Logic Unit [PLU]Parallel PortParallel Processor Command InterfaceParallel Processor [PP]Parallel TransfersParameter RAMParameter TableParserPartial LinkingPatchPC RegisterPending InterruptPeriodic EventPeriod [PRD] RegisterPeripheral BusPeripheral CablePeripheral Component Interconnect [PCI]Personal Computer [PC]Phase Alternation Line [PAL]Phase DetectorPhase-Frequency Detector [PFD]Phase-Locked Loop [PLL]Phase Margin [Ø]Phase NoisePhase Noise FloorPhysical AddressPin Grid Array [PGA]Pin-to-Pin On Resistance [RON]PipelinePipelined-Loop EpilogPipelined-Loop PrologPipelined ModePipeline StallPipeliningPitchPixelPixel-Block Transfer [PIXBLT]Pixel DroppingPlayback ModePointPollPOPPorchPortPort AddressPort IDPort TablePostscalerPower-Down ModePower Management Unit [PMU]Power-On Reset [POR]Power-Supply Rejection RatioPower Transmitting and Power Receiving [Tx], [Rx]PragmaPreemptPrefetch Counter [PFC]PreprocessorPrescalerPrescaler Counter [PSC]Present FlagPrinted-Circuit Assembly [PCA]Private ContextProcessorProcessor Mode Status Register [PMST]Processor NodeProduct Register [PREG]Product-Scaling ShifterProduct Shift Mode [PM] BitsProfile WindowProfilingProgram Address Bus [PAB]Program-Address Generation LogicProgram Address Register [PAR]Program ControllerProgram Control LogicProgram Counter [PC]Program Counter [PC] FieldProgram/Data Wait-State Register [PDWSR]Program Flow Control UnitProgram-Level OptimizationProgrammable Logic Array [PLA]Programmable Read-Only Memory [PROM]Programmed I/O [PIO] ModeProgram MemoryProgram Memory Address [PMA]Program Read Bus [PRDB]Program Select Pin [PS]Program-Space Upper Wait-State [PSUWS] BitProgram-Space Wait-State [PSWS] BitPrologProtected ModePulldown MenuPulse Coded Modulation Mode [PCM] BitPulse Code Modulation [PCM]Pulse Frequency Modulation (or Mode) [PFM]Pulse Width Modulation [PWM]PushPx64QiQuality Factor [Q]Quantization ErrorQuantum LevelsQuick Output Discharge [QOD]Quiet Not-a-Number [QNaN]Quiet RunRadio Frequency Front End [RFFE]RAM Enable Pin [RAMEN]RAM ModelRAM Overlay (OVLY) bitRandom-Access Memory Digital-to-Analog Converter [RAMDAC]Random-Access Memory [RAM]RasterRaster-OpRaw dataRCA ConnectorRCA JackR DividerRead-Only Memory [ROM]Read Select Pin [RD]Read/Write [R/W] PinReadyReadyReady QueueReal ModeReal TimeReal-Time ProcessingReal-Time SystemReceive Buffer Half Received [RH] BitReceive Clock Input (CLKR) PinReceive [DR] Pin (Synchronous Serial Port)Receive FIFO Buffer Not Empty [RFNE] BitReceive Frame Synchronization [FSR] PinReceive Interrupt (Asynchronous Serial Port)Receive Interrupt Mask Bit [RIM]Receive Interrupt (Synchronous Serial Port) [RINT]Receive Ready [RRDY] BitReceive Register (Asynchronous Serial Port) [ADTR]Receive Register (Synchronous Serial Port) [SDTR]Receive Reset [RRST] BitReceiver Register Overrun Indicator Bit [OE]Receiver Reset [RRST] BitReceiver Reset [RRST] BitReceive [Rx]Receive [RX] Pin (Asynchronous Serial Port)Receive Shift Register (Synchronous Serial Port) [RSR]Receive (Synchronous Serial Port) [DR] PinReclamation PortReconnectReduced Instruction Set Computer [RISC]Redundant LoopsReentrant CodeReference SpursRefreshRefresh RateRegisterRegister FileRelative AccuracyRelocationRemote Procedure Call [RPC]Repeat Counter [RC] RegisterRepeat ModeReply MessageReply PortRequest MessageReserved [R]ResetReset Asynchronous Serial Port [URST] BitReset Pin (RS)Reset VectorResolutionResolution Bandwidth [RBW]Resource IDResource TableResumeRetraceReturn AddressReverse AssemblyReverse Current Blocking [RCB]Reverse Current Protection [RCP]Rightmost 1 [rmo]Rightmost-Bit Change [rmbc]Ripple-Carry Output SignalRom Enable [ROMEN]ROM ModelROM WidthRoot Mean Square [RMS] or [rms]Round-Robin SchedulingRouting PortRow Address Strobe [RAS]Run AddressRuntime EnvironmentRuntime-Support FunctionsRuntime-Support LibrarySAM Overflow EventSample RateScalar TypeScan ChainSchedulerSchedulingScratch-Pad RAMScriptScrollingSCSISCSI AddressSCSI DeviceSCSI IDSectionSection HeaderSection Program Counter [SPC]SemaphoreSemaphore IDSemaphore TableSemi-Omnipresent PixelSensitivitySequential ModeSerial Access Memory Increment [SAMINC]Serial Access Memory Mask [SAMMASK]Serial Access Memory [SAM]Serial Clock [SCLK]Serial Data Receive [DR] PinSerial Data Transmit [DX] PinSerial PortSerial-Port InterfaceSerial Port Receive Interrupt [RINT] BitSerial Port Transmit Interrupt [XINT] BitSerial Register Transfer [SRT] ControllerServerSetbrk BitShared-Access Mode [SAM]Shared-Access Mode [SMOD] BitShared RAMsShell ProgramShifterShort-Floating-Point FormatShort ImmediateShort-Immediate ValueShort Integer FormatShort OffsetShort Unsigned-Integer FormatSide EffectsSignalSignal EventSignaling Not-A-Number [SNaN]Signal-To-Noise Ratio [SNR]Sign BitSign-ExtendSign ExtensionSign-Extension Mode Bit [SXM]SimulatorSingle-Access RAM [SARAM]Single Ended [SE]Single-Precision Floating-PointSingle-Precision Floating-Point FormatSingle-Precision Integer FormatSingle-Precision Unsigned-Integer FormatSingle StepSingle ThreadedSkewSlew RateSmall Outline (no lead) [SON]Smith ChartSoft BitSoftware Development System [SWDS]Software PipeliningSoftware StackSoftware WriteSource FileSpectrum AnalyzerSpinningSplit ModeSplit MultiplySpur Gain [SG]Spurious AttenuationSram BanksStackStack PointerStandalone PreprocessorStandalone SimulatorStart BitStateStatic Random-Access Memory [SRAM]Static VariableStatusStatus BitStop BitStorage ClassString TableStructureSub-BlockSub-Block MissSubroutineSubsectionSubstitution Symbol TableSuper VHS (Vertical Helical Scan) [S-VHS]Supervisor ModeSuspendS-VHS-to-RCA Adapter CableSwap FileSwitch Mode Power Supply [SMPS]SymbolSymbolic DebuggingSymbolic DebuggingSymbol TableSyncSynchronous Power ConverterSynchronous Serial Port Receive InterruptSyntaxSystem ShellT31 RatioT41 RatioT43 RatioTagTap PointTargetTarget MemoryTARGET SystemTaskTask ArgumentTask DescriptorTask ErrorTask FunctionTask IDTask InterruptTask PriorityTask SchedulerTask StateTask TableTDM Address [TADD]TDM Clock [TCLK]TDM Data [TDAT]TDM Receive Interrupt (TRNT) BitTDM Transmit Interrupt (TXNT) BitTemperature-Compensated Crystal Oscillator [TCXO]Test Access Port [TAP]Test and Control (TC) Flag Bit.Text SectionThread of ExecutionTightly-Coupled MultiprocessorTime-Division Multiplexed [TDM]Time-Division Multiplexed (TDM) BitTime-Division Multiplexing [TDM]TimerTimer Divide-Down Register [TDDR] BitsTimer Interrupt [TINT]Timer Interrupt [TINT] BitTimer Output [TOUT] PinTimer Prescaler Counter [PSC] BitsTimer Reload [TRB] BitTimer Stop Status [TSS] BitTime SlicingTop Of Stack [TOS]Total Harmonic Distortion And Noise [THD+N]Totem-Pole OutputTransfer Controller [TC]Transient Voltage Suppressor [TVS]Transmission Control [TCOMP] bitTransmit and Receive InterruptTransmit Buffer Half Transmitted [XH] BitTransmit Clock I/O [CLKX] PinTransmit Empty Indicator [TEMT] BitTransmit Frame Synchronization [FSX] PinTransmit Interrupt Mask [TIM] BitTransmit Interrupt Serial PortTransmit Interrupt [XINT] Synchronous Serial PortTransmit Mode [TXM] BitTransmit Ready [XRDY] BitTransmit Register Empty Indicator [THRE] BitTransmit Reset [XRST] BitTransmit Shift Register Empty [XSREMPTY] BitTransmitter Reset [XRST] BitTransmit [Tx]TransparencyTransparency on Source OperationTrapTrap Vector Table Pointer [TVTP]Trap Vector Table [TVT]Trickle Refresh CyclesTri-Graph SequenceTrip CountTripleUnconfigured MemoryUnder-Voltage Lockout [UVLO]Unified ModeUninitialized SectionUnionUnionUniversal Asynchronous Receiver and Transmitter [UART]Unsigned ValueUrgent Refresh CyclesUser ModeVaractor DiodeVariableVariable-Patch Guided TransferVector Dot ProductVector InstructionVendor Unique [VU]Vertical Blanking [VBLNK]Vertical Synchronization [VSYNC]VGA Pass-Through CableVideo ControllerVideo DigitizerVideo Graphics Array [VGA]Video Interface Palette [VIP]Video Random Access Memory [VRAM]Virtual MemoryVoltage-Controlled Crystal Oscillator [VCXO]Voltage-Controlled Oscillator [VCO]Voltage-Controlled Oscillator (VCO) Gain [KVCO]Wafer Chip-Scale Package [WCSP]WaitingWait QueueWait StateWait-State GeneratorWarm BootWATCH WindowWell-Defined ExpressionWindowWordWrite Enable [WE] PinXA0-XA13 Address PinsXD0-XD31 Data Bus PinsZero-Code ErrorZero-Code Error DriftZero Fill
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Date
2016-03-01
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